The present invention relates to the field of semiconductor devices and, in particular, to charge storage structures of memory devices.
A dynamic random access memory (DRAM) cell typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET applies or removes charge on the capacitor, affecting therefore a logical state defined by the stored charge. The conditions of DRAM operations, such as operating voltage, leakage rate and refresh rate, will generally mandate that a certain minimum charge be stored by the capacitor. In the continuing trend to higher memory capacity, the packing density of storage cells must increase, yet each must maintain required capacitance levels for a respective memory cell area. Accordingly, it is becoming extremely difficult to produce a capacitor with a relatively high storage capacitance on the available memory cell area.
With a view towards further miniaturization of electronic devices, single-electron components have been introduced, in which switching processes are effected with single electrons. This way, techniques for memory systems in silicon technology based on (1) trapping of single electrons on silicon inclusions in the gate oxide of transistors; (2) trapping of electrons at traps or point defects in the gate oxide; (3) trapping of electrons on the grains of polysilicon in thin film transistors; or (4) trapping of single electrons in potential minimum regions in an ultra-thin film of roughened silicon on insulator material have been disclosed. Most of these techniques, however, involve the tunneling of electrons through thin oxides, which in turn requires high electric fields in such oxides. Such high electric fields degrade the oxides and confer only a limited number of memory cycling times, typically in the order of 109 times. Other single-electron techniques involve the trapping of electrons on polysilicon grains formed in thin film devices, but this process is difficult to control since the roughening of the polysilicon to form the grains occurs randomly.
Accordingly, there is a need for an improved method of forming single-electron devices used in IC fabrication. There is also a need for high density single-electron memory devices with conduction channels and storage areas which are easily reproducible and which do not occur in a random manner, as well as a method for fabricating such memory devices.
The present invention provides a method for forming edge-defined structures with sub-lithographic dimensions which are used to further form conduction channels and/or storage structures in single-electron memory devices.
In an exemplary embodiment of the invention, sacrificial silicon nitride islands are deposited at low temperatures and then patterned and etched by high resolution etching techniques. Polysilicon is next deposited over the sacrificial silicon nitride islands and directionally etched to form edge-defined polysilicon dot and strip structures which are about one tenth the minimum feature size.
In an exemplary embodiment of the invention, edge-defined polysilicon strips and dots are formed between the source and drain region of an NMOS device. Subsequent to the removal of the sacrificial silicon nitride islands, the edge-defined polysilicon strips and dots are used to mask a threshold voltage implantation in a conventional CMOS process. This way, a conduction channel and two adjacent potential minimum dots are formed after the removal of the edge-defined polysilicon strips and dots. The presence or absence of electrons in these potential minimum dots will modulate the number of electrons in the conduction channel of, for example, a single-electron DRAM of very high density.
Additional advantages of the present invention will be more apparent from the detailed description and the accompanying drawings, which illustrate exemplary embodiments of the invention.